1. Field of the Invention
The present invention relates to processor system buses, and more particularly to a technique for dynamically adjusting the time at which data on system bus is sampled and provided to a microprocessor core, where the time is based not upon guaranteed data valid time, but upon detection of source synchronous data strobe edges.
2. Description of the Related Art
A present day sampled data bus, such as may be employed in a microprocessor or integrated circuit (IC) device that communicates over a system bus with other devices to exchange data, receives data from the system bus via data signals. The data signals are indicated as being on the system bus via a data ready signal DRDY that is asserted by the device that is sending the data. The data and DRDY signals are typically asserted and de-asserted in synchronization with a bus clock signal BCLK. According to present day bus protocol, when the sending device drives data onto the data bus, it asserts DRDY, and the states of the data bus signal are guaranteed as being valid on the bus for sampling one cycle of the BCLK later. Accordingly, a present day microprocessor or integrated circuit that is required to receive the data must wait for one cycle of the bus clock BCLK before it samples the data.
Newer protocols for communication of data over a system bus have provided for source synchronous data strobes. The current state of the art provides for a 64-bit data bus DATA that supports transfer during the data phase of a 64-byte cache line over two cycles of a dual bus clock signal BCLK. The transfer of eight bytes over the 64-bit data bus is known as a beat and 4 beats are transferred during each cycle of the bus clock BCLK. In an x86-compatible configuration, the data bus signal group is divided into four subgroups and a pair of data strobes are provided for each data subgroup. Applicable edges (e.g., the falling edges) of each data strobe are used to indicate validity of corresponding words asserted on corresponding subgroups of data.
The present inventor has observed that if conventional techniques for sampling the data signals over a system bus as described herein are employed, disadvantages ensue. First, since four quadwords are transmitted during the BCLK cycle following transmission of another four quadwords, to wait for 1 BCLK cycle before sampling the data would result in unpredictable sampling results. Second, since data strobes are provided to indicate validity of their corresponding doublewords on the data bus, to wait 1 cycle of BCLK before sampling is disadvantageous from a performance standpoint.
It is desired to solve the problem of delay when providing received data elements from a system bus to a processor core due to protocol requirements for data valid times.